Turning to FIG. 1 of the drawings, a conventional two-stage amplifier system 100 can be seen. System 100 generally comprise a first stage 102 and a second stage 104 (which are each generally inverting amplifiers). As can be seen, resistor networks (resistors R1/R1 and resistors R3/R4) are coupled between the negative input terminals and output terminals of operational amplifiers 106 and 108, respectively, so that stage 102 can receive the input signal VIN and that stage 104 can receive output signal VOUT1. Additionally, offset voltage source 110 and 112 provide offset voltages VOS1 and VOS2 to operational amplifiers 106 and 108, respectively. Each of the voltage sources 110 and 112 (which include the internal offsets of amplifiers 106 and 108) are also coupled to supply rail 114 (which is generally at ground).
Because of the configuration of system 100 offset and noise contributions from voltage source 110 can significantly affect the output signal VOUT2. For the amplifier stage 102, output signal VOUT1 can be represented as follows:
                              VOUT          ⁢                                          ⁢          1                =                                                                              -                  R                                ⁢                                                                  ⁢                2                                            R                ⁢                                                                  ⁢                1                                      ⁢                          (                              VIN                -                                  VOS                  ⁢                                                                          ⁢                  1                                            )                                +                      VOS            ⁢                                                  ⁢            1                                              (        1        )            Additional, amplifier stage 104, output signal VOUT2 can be represented as follows:
                              VOUT          ⁢                                          ⁢          2                =                                                                              -                  R                                ⁢                                                                  ⁢                4                                            R                ⁢                                                                  ⁢                3                                      ⁢                          (                                                VOUT                  ⁢                                                                          ⁢                  1                                -                                  VOS                  ⁢                                                                          ⁢                  2                                            )                                +                      VOS            ⁢                                                  ⁢            2                                              (        2        )            Now, substituting equation (1) into equation (2), output signal VOUT2 becomes:
                                                        VOUT              ⁢                                                          ⁢              2                        =                                                                                                                              -                        R                                            ⁢                                                                                          ⁢                      4                                                              R                      ⁢                                                                                          ⁢                      3                                                        ⁢                                      (                                                                                                                                                      -                              R                                                        ⁢                                                                                                                  ⁢                            2                                                                                R                            ⁢                                                                                                                  ⁢                            1                                                                          ⁢                                                  (                                                      VIN                            -                                                          VOS                              ⁢                                                                                                                          ⁢                              1                                                                                )                                                                    +                                              VOS                        ⁢                                                                                                  ⁢                        1                                            -                                              VOS                        ⁢                                                                                                  ⁢                        2                                                              )                                                  +                                  VOS                  ⁢                                                                          ⁢                  2                                            =                                                                                          R                      ⁢                                                                                          ⁢                                              4                        ·                        R                                            ⁢                                                                                          ⁢                      2                                                              R                      ⁢                                                                                          ⁢                                              3                        ·                        R                                            ⁢                                                                                          ⁢                      1                                                        ⁢                  VIN                                +                                                                                                    -                        R                                            ⁢                                                                                          ⁢                      4                                                              R                      ⁢                                                                                          ⁢                      3                                                        ⁢                                      (                                          (                                                                                                    R                            ⁢                                                                                                                  ⁢                            2                                                                                R                            ⁢                                                                                                                  ⁢                            1                                                                          +                        1                                            )                                        )                                    ⁢                  VOS                  ⁢                                                                          ⁢                  1                                -                                  VOS                  ⁢                                                                          ⁢                  2                                                              )                +                  VOS          ⁢                                          ⁢          2                                    (        3        )            Equation (3) can also be expressed as a function of offset voltage VOS1 (where offset voltage VOS2 is about 0):
                              VOUT          ⁢                                          ⁢          2                =                                                            R                ⁢                                                                  ⁢                                  4                  ·                  R                                ⁢                                                                  ⁢                2                                            R                ⁢                                                                  ⁢                                  3                  ·                  R                                ⁢                                                                  ⁢                1                                      ⁢            VIN                    +                                                                      -                  R                                ⁢                                                                  ⁢                4                                            R                ⁢                                                                  ⁢                3                                      ⁢                          (                                                                    R                    ⁢                                                                                  ⁢                    2                                                        R                    ⁢                                                                                  ⁢                    1                                                  +                1                            )                        ⁢            VOS            ⁢                                                  ⁢            1                                              (        4        )            When resistor R1 is coupled to a block capacitor (AC coupled), the input signal VIN is equal to offset voltage VOS1, reducing equation (3) as follows:
                              VOUT          ⁢                                          ⁢          2                =                                                                                                  -                    R                                    ⁢                                                                          ⁢                  4                                                  R                  ⁢                                                                          ⁢                  3                                            ⁢                              (                                                      VOS                    ⁢                                                                                  ⁢                    1                                    -                                      VOS                    ⁢                                                                                  ⁢                    2                                                  )                                      +                          VOS              ⁢                                                          ⁢              2                                =                                                    (                                  1                  +                                                            R                      ⁢                                                                                          ⁢                      4                                                              R                      ⁢                                                                                          ⁢                      3                                                                      )                            ⁢              VOS              ⁢                                                          ⁢              2                        -                                                            R                  ⁢                                                                          ⁢                  4                                                  R                  ⁢                                                                          ⁢                  3                                            ⁢              VOS              ⁢                                                          ⁢              1                                                          (        5        )            So, it can clearly be see from the DC coupled and AC coupled cases of equations (3) through (5), respectively, that noise and offset contributions in output voltage VOUT2 from offset voltage VOS1 can be significant. Thus, system 100 may require the use of trim circuit or better device matching to reduce the noise and offset contributions from offset voltage VOS1.
Some other conventional designs are: U.S. Pat. No. 3,899,743; U.S. Pat. No. 5,257,285; U.S. Pat. No. 6,642,783; U.S. Pat. No. 7,132,882; and U.S. Patent Pre-Grant Publ. No. 2006/0279344.